1. Field of the Invention
The present invention relates to a method of evaluating reliability of a TFT (Thin Film Transistor) and, more specifically, to a method of evaluating reliability of a TFT including a channel layer of silicon thin film and a gate insulating film of silicon oxide.
2. Description of the Background Art
In an SRAM (Static Random Access Memory) device, it is possible to retain data for a long period of time by using a battery. One of the important factors representing the performance of this device includes a so called "hold lower limit voltage". The hold lower limit voltage means the lower limit value of the voltage at which the data can be correctly held in the SRAM device.
FIG. 14 shows an example of an equivalent circuit of an SRAM cell. The SRAM cell includes a pair of storage nodes 10a and 10b; a pair of load transistors 11a and 11b; a pair of driver transistors 12a and 12b; a pair of access transistors 13a and 13b; a pair of bit lines 14a and 14b; and a pair of word lines 15a and 15b. More specifically, in the SRAM cell, data is stored by a flipflop including two driver transistors 12a and 12b as well as two load transistors 11a and 11b by maintaining one storage node at H (high) level and maintaining the other storage node at L (low) level.
Now, assume that the storage node 10a is at H level. Then, load transistor 11a is ON, while driver transistor 12a is OFF. In other words, the state in which storage node 10a is at the H level corresponds to the state in which ON current of load transistor 11a is larger than the OFF current of driver transistor 12a.
Recently, load transistors of the SRAM cells increasingly come to be manufactured by using TFTs. However, in an SRAM cell including a TFT load transistor, ON current of load TFT 11a gradually reduces while it is used retaining data for a long period of time, and eventually it becomes smaller than the OFF current of driver transistor 12a. As a result, data at the H level may possibly be erroneously replaced by L level. The problem causing such an error is referred to as "hold defect". In order to avoid hold defect in the SRAM cell, it is necessary to well understand the properties of the TFT in which ON current decreases during use over a long period of time.
When the SRAM cell holds data, the load TFT on the side of the storage node 10a which is at the H level, is at such a voltage state as shown in FIG. 15 (A). In FIG. 15(A), a reference character V.sub.S represents source voltage, V.sub.D represents drain voltage, V.sub.G represents gate voltage and Vcc represents power supply voltage. The voltage state of the TFT shown in FIG. 15(A) is equivalent to the voltage state shown in FIG. 15(B). The voltage state of the TFT shown in FIG. 15(B) is referred to as "-BT stress state."
Degradation in the TFT characteristic caused by -BT stress is reported in detail by Maeda et al., in J. Appl. Phys., Vol. 76 (12), 1994, pp. 8160-8166. According to this article of Maeda et al., threshold voltage of the TFT shifts in the negative direction by the -BT stress, as shown in FIG. 16. More specifically, in FIG. 16, the abscissa represents gate voltage V.sub.G while the ordinate represents drain current I.sub.D in logarithmic scale. Curves 16A and 16B represent characteristics of TFT before and after -BT stress. The inventors of the present invention disclosed a method of accurately predicting an amount of shift of the threshold voltage of the TFT caused by -BT stress in Japanese Patent Laying-Open No. 6-326315. If the amount of shift of the threshold voltage is predicted in accordance with the method disclosed in Japanese Patent Laying-Open No. 6-326315 and if initial threshold voltage of the TFT is set appropriately in advance, it is possible to provide an SRAM device which does not suffer from hold defect even after it holds data for a long period of time.
However, the channel layer of the TFT is formed of a polycrystalline silicon thin film, and therefore among a plurality of TFTs manufactured under the same manufacturing conditions, initial characteristics of the TFTs vary as shown in FIG. 17. In addition, characteristics after -BT stress also vary widely, because of vibration in density of crystal grain boundary in the channel layer. Therefore, in the SRAM device, there is a high possibility of hold defect after it holds data for a long period of time, unless the amount of shift of the threshold voltage of the TFT having worst performance after -BT stress is estimated.
Conventionally, a TFT having a polycrystalline silicon thin film of which crystal grain diameter is relatively small with respect to the channel length has been used in the SRAM. Therefore, variation in the characteristics of the TFTs such as shown in FIG. 17 is small. Therefore, estimation of the amount of shift of the threshold value in the TFTs in accordance with the method disclosed in the aforementioned Japanese Patent Laying-Open No. 6-326315 has been sufficient. However, in order to minimize the size of the TFT, channel length becomes shorter, while the crystal grain diameter of the polycrystalline thin film is made larger in order to increase drain current. Accordingly, variation of the grain boundary density of polycrystalline silicon in the channel layer becomes larger in the individual TFT, and variation in the characteristics of TFTs becomes innegligible. Variation in the characteristics of TFTs caused by the dimensional relation between the grain diameter of polycrystalline silicon and the channel length is described in detail by Noguchi in Jpn. J. Appl. Phy., Vol. 32, 1993, pp. L1584-L1587.
Now, -BT stress degradation of TFT characteristics is closely related to dangling bond density and ratio of hydrogenation of silicon atoms in a polycrystalline silicon thin film. The dangling bond density and the ratio of hydrogenation of a polycrystalline silicon film by itself can be measured by using an ESR (Electronic Spin Resonance) apparatus. However, the dangling bond density and the ratio of hydrogenation of a polycrystalline silicon film in a finished TFT cannot be measured by the ESR apparatus. Therefore, there is a strong demand for development of a method of easily estimating the dangling bond density and the ratio of hydrogenation in the polycrystalline silicon thin film in a finished TFT.